1. Field of the Invention
The invention generally relates to a semiconductor device, and more particularly, to a method for insulating wires of a semiconductor device.
2. Background of the Invention
With increase in an integration degree of semiconductor devices, a design rule of circuit wires such as a bit line has been sharply decreased. For example, as a design rule of a Dynamic Random Access Memory (DRAM) device is decreased to below 40 nm and a design rule of 34 nm is required, a method for filling a gap between bit lines to effectively insulate the bit lines is required. Because a critical dimension of the bit line has been sharply decreased, it becomes difficult for an interlayer insulation layer to effectively fill the gap between the bit lines.
To form the interlayer insulation layer, a process of depositing High Density Plasma (HDP) insulation between the bit lines has been used. However, as an aspect ratio of the gap between the bit lines is increased with decrease in the design rule, it becomes difficult to effectively fill between the bit lines with a HDP insulation layer. Moreover, in a DRAM device, the aspect ratio of the gap between the bit lines has been greatly enlarged as a capping layer introduced above the bit line is gradually thickened and a spacer is introduced on a side wall of the bit line. This capping layer is required to be formed with larger thickness because it is used as an etch barrier in a subsequent process of forming a self aligned contact hole. As the aspect ratio of the gap between the bit lines is increased as such, it becomes more difficult to fill between the bit lines with the HDP insulation layer. Therefore, it is required to develop a method of forming an interlayer insulation layer which fills and insulates between the bit lines more effectively.